1. Field of the Invention
The invention relates generally to methods and apparatus used for transferring data to and from a first bus, to which a first set of high performance devices, including a central processor ("CPU") is attached, and a second bus, to which a second set of relatively lower performance devices is attached, in a manner that does not limit the CPU's performance. The invention more particularly relates to a novel data transfer controller ("DTC"), or set of DTC's, suitable for performing the aforesaid data transfer function between a high performance channel, hereinafter referred to as the "Local Bus", to which a CPU constituting a part of a reduced instruction set computer (RISC) system is attached, and one or more, typically lower performance, peripheral buses, each hereinafter referred to as a "Remote Bus".
2. Description of the Related Art
Methods and apparatus for achieving a high performance system interface between a RISC processor and a set of devices, including memory means internal to the RISC system, are described in copending application Ser. No. 012,226, filed Feb. 19, 1987, now U.S. Pat. No. 4,851,900, assigned to Advanced Micro Devices, Inc. This copending application is hereby incorporated by reference. The novel system interface taught in the copending application includes, according to its preferred embodiment, two 32 bit wide buses referred to as the "Address Bus" and "Data Bus". For the purpose of this application these two buses collectively correspond to the Local Bus.
In order to permit a RISC system to utilize and access a wide array of commercially available peripheral devices that typically operate at lower speeds than a RISC processor, the Local Bus needs to be coupled in some manner to a Remote Bus to which one or more of said peripheral devices are connected. The Remote Bus could also be a complete I/O subsystem with its own processor.
Currently, no devices or methods are known which interconnect and permit data transfers between buses having different performance characteristics (like the aforesaid Local Bus and Remote Bus), while at the same time not appreciably having an affect on the performance of the devices attached to the buses. In addressing this problem it would be a particularly desirable feature to insulate the performance of any high speed processor, e.g., a RISC processor attached to the Local Bus, from the comparatively lower performance of peripherals and/or any I/O subsystem connected to the Remote Bus. Ideally, the bandwidth and latency of accesses on the Local Bus needs to be decoupled from the bandwidth and latency of accesses on the Remote Bus, with concurrency between accesses on both buses.
Another problem to be solved is to provide methods and apparatus which allow I/O port and direct memory access ("DMA") operations to overlap with (i.e., operate in parallel with) devices attached to the Local Bus. Such a parallelism feature would further enhance the performance of the overall system of which the DTC forms a part and more particularly, in a RISC system, would free the RISC processor from having to wait for I/O completion.
I/O controller functions and DMA functions in and of themselves are well known in the prior art. However no combination of these functions are performed by any known methods or apparatus which, (1) interconnect and buffer a high performance RISC system Local Bus and a Remote Bus of the type described hereinbefore; (2) solve the aforementioned problem of interconnecting buses having different performance characteristics and (3) provide the parallelism referred to hereinbefore.
Furthermore, no DMA channel by itself is known which supports a bus to bus interface of the type described hereinabove, i.e., a DMA channel which accounts for differing bus characteristics and parallelism versus a DMA channel that only performs straight address sequencing.
Finally, although systems, such as the IBM 370 (a large main frame computer) are known that include a channel controller network with direct memory access features, no prior art is known at the microprocessor level, in particular in combination with a RISC processing system, that provides both DMA and I/O controller functions on a single chip. Such features would be a desirable adjunct to RISC processing systems which themselves are currently being fabricated at the chip level.